What launched
3× WSE
A rack‑scale CS‑4 system with three WSE‑3 Turbo, not a single isolated chip.
Edition 2.0 · information cutoff: U.S. regular session of August 18, 2026 and publications available through the early hours of August 19 (UTC−5). Market figures may change after this cutoff.
TECHNICAL + FINANCIAL + PATENT ATLAS
Cerebras CS‑4
taken apart piece by piece
An explanation from absolute zero —from the transistor and the wafer through GPT‑5.6, the cloud, the contracts, the patents and the stock price— rigorously separating facts, vendor claims, derived calculations, forward-looking targets and data still unpublished.
Primary sources
SEC / finance
Independent literature
Interactive simulators
3×WSE‑3 Turbo per system
750sparse FP16 PFLOPS, aggregate peak
129.6PB/s of aggregate SRAM bandwidth
Conclusion in one sentence: CS‑4 is a serious engineering advance for low-latency inference, but economic value depends on converting laboratory speed into deployed capacity, utilization, margin, reliability and cost per token.
01 · Researchprimary sources and timeline
02 · Engineeringarchitecture and bottlenecks
03 · Auditmethodology and counterexamples
04 · Correctionpedagogy and internal coherence
Nexus chassis
Stable infrastructure —power, cooling and I/O— is separated from three replaceable compute modules. The drawing is pedagogical, not a CAD blueprint.
01
The map before entering the forest
Executive verdict in 90 seconds
The six ideas that keep you from confusing speed, capacity, efficiency, model size, revenue and the stock price.
Speed per user
up to 2×
Each Turbo wafer can generate tokens up to twice as fast as the previous generation.
System peak
6×
125 → 750 PFLOPS sparse FP16: three wafers multiplied by ~2× each.
Stated efficiency
up to 10×
Total throughput per watt versus CS‑3; it does not mean a ten times smaller electricity bill.
Versus GPU
up to 30×
Tokens/s per user in selected cases; it is a vendor maximum, not a universal law.
GPT‑5.6 Sol
≈1.2–1.4k
The chart figure is speed in tokens/s, not a price in dollars.
What matters most: 650, 750, 1,200 or 1,400 describe approximately how many output tokens per second the system produces. The model tariff is expressed in dollars per million tokens. They are completely different units.
What does change
The wait during generation, how many users an installation can serve, the viability of agents that run many steps, and the potential economics of the data center.
What is still unproven
Rack price, total power, cost per million tokens on CS‑4, large-volume availability, fleet reliability, real utilization, gross margin and a normalized TCO comparison against GB300/MI455X.
02
Foundations
From absolute zero: what is happening when an AI “speaks”
Understanding this section makes all later figures make sense.
1. Token
A token is a small unit of text: it can be a short word, part of a word, a sign or a fragment of code. The model does not write a page all at once; it predicts one token, then another, and so on.
“Cerebras” ≈ several fragments1,000 tokens ≈ 700–800 words, very approximate
2. Inference
It is using an already-trained model to answer. Training builds the “brain”; inference puts it to work. CS‑4 is aimed especially at ultra-fast inference and at enormous models.
3. Tokens per second
They measure output speed once the answer has started. At 100 t/s, 1,000 tokens take about 10 s; at 1,000 t/s, about 1 s. They do not necessarily include prior reasoning, network, or tool time.
PromptYour text enters
→
PrefillReads the full context in parallel
→
DecodeProduces token by token
Analogy: prefill is reading and understanding the full file; decode is dictating the answer word by word. The first phase favors a lot of parallel computation; the second is heavily constrained by moving weights and state with minimum latency.
TTFT versus output speed
Time to First Token is how long you wait to see the first token. Output tokens/s is how fast the rest comes out. A system can have 1,200 t/s and still feel slow if prior reasoning takes 30 seconds.
Latency versus throughput
Latency: time of a single request. Throughput: total work of the whole system. A restaurant can serve one table very fast but few tables, or many tables with more waiting. CS‑4 claims to improve both axes.
03
Product
What CS‑4 actually is
The name groups processors, rack, power, cooling, network and software.
CS‑4 = 3 Turbo wafers + Nexus + power + cooling + I/O + software
It should not be imagined as a “giant graphics card”. It is an active rack system with three compute modules —the Wafer-Scale Backpacks— installed on a power and cooling platform. Each backpack contains a WSE‑3 Turbo and the subsystems needed to operate it.
It is not a consumer product. It is not bought like an RTX for a PC. It is aimed at hyperscalers, data centers, governments and enterprises that deploy infrastructure; the page refers to commercial contact and does not publish a rack price.
Processors
3
WSE‑3 Turbo per system.
Transistors
12 T
3 × 4 trillion (trillion, short scale) physical aggregated.
AI cores
2.7 M
3 × 900,000, aggregated.
Physical SRAM
132 GB
3 × 44 GB; do not automatically assume a single flat address space.
| Official metric | CS‑4 system | Per WSE‑3T wafer | Plain translation |
|---|---|---|---|
| AI compute | 750 PFLOPS* | 250 PFLOPS* | Theoretical peak in sparse FP16; it is not guaranteed performance of an application. |
| Memory bandwidth | 129.6 PB/s | 43.2 PB/s | Speed at which cores access the distributed SRAM on wafer. |
| Fabric bandwidth | 160.5 PB/s | 53.5 PB/s | Communication capacity within the compute fabric. |
| External I/O | 7.2 Tbit/s | 2.4 Tbit/s | Input/output to connect to other systems and data. |
| Wafer-to-wafer latency | up to 2 μs | — | Two millionths of a second on the announced direct link. |
| Process | 3 wafers | TSMC 5 nm | The jump does not come from moving to 3 nm, but from system, power, and frequency. |
*The datasheet specifies “sparse FP16”. Comparing this number with a GPU’s FP4 or FP8 without normalizing precision and sparsity would be incorrect. Official sources: O1, O2.
How can it “support more than 50 trillion parameters” if there are only 44 GB per wafer? “Support” does not mean storing all dense weights inside that SRAM. Large models are partitioned and their weights/states can be distributed or streamed through a larger infrastructure. Also, in MoE models only a fraction of the parameters is activated per token. Cerebras has not published on these pages all implementation details of a 50T model.
04
Interactive teardown
CS‑4, component by component
A rack is not “a big chip”. It is a coordinated chain of compute, memory, power, cooling, network and software.
Core idea: Nexus tries to make refreshing compute not require rebuilding the entire rack. That modularity can shorten installation, service and upgrade cycles; public data on total cost and fleet maintenance are still missing.
Conceptual visualization based on official descriptions. It does not represent exact internal dimensions, flow trajectories or a manufacturing schematic.
05
Disambiguation
Why 2×, 6×, 10× and 30× can all be true at once
Each multiplier uses a different denominator. Mixing them produces false conclusions.
2×
Peak speed per wafer versus WSE‑3
The WSE‑3 Turbo receives more power and runs at higher frequency. It is the generational comparison closest to “an answer comes out twice as fast”. Official
6×
Aggregate system resources versus the single-wafer CS‑3
Three wafers × approximately twice the compute per wafer = 750 PFLOPS versus 125. Memory, fabric and I/O also show around six times the total. Derivado de ficha
10×
Throughput per watt versus CS‑3
It measures sustained total tokens within an energy budget, not the speed of a single conversation. Absolute power, workload and complete methodology are missing to reproduce it. Vendor claim
30×
Tokens/s per user versus selected GPU systems
It is “up to”, and it depends on model and configuration. It does not mean 30× more quality, 30× cheaper or 30× faster in training. Vendor claim
>1k
Tokens/s on models larger than 10T parameters
The company attributes this result to 2 μs wafer‑to‑wafer latency. The exact model, precision, length and methodology are not fully detailed on the public page. Vendor claim
Common error: claiming “CS‑4 is 30 times better than NVIDIA”. The correct sentence is: “Cerebras states up to 30× more tokens per second per user than certain production GPU systems, under internal or third-party tests that vary by model and configuration”.
Economic reading
To monetize, a 2× faster answer is not enough. The company needs to combine speed, high utilization, many concurrent users, attractive prices and an infrastructure investment that does not destroy margin. The simplified formula is:
Revenue ≈ deployed capacity × utilization × billable tokens × price per token
And margin subtracts hardware depreciation, data-center rent, energy, network, maintenance, staff and financing costs.
06
The 650 → 1,200 confusion
GPT‑5.6 Sol: speed is not price
This is the point most easily misread.
What the figures mean
≈650 t/s: possible sustained speed observed by users in the first implementation.
up to 750 t/s: official public figure for GPT‑5.6 Sol Ultrafast on Cerebras before CS‑4.
≈1,200–1,400 t/s: shown/communicated range for GPT‑5.6 Sol on CS‑4. The official chart looks near 1,400; a verbal figure of 1,200 may be rounded, sustained, or use another condition.
They are not dollars. API prices are published in $ per million tokens. The public GPT‑5.6 page lists Sol at $5/M input and $30/M output; the specific/commercial price of the Ultrafast preview or of CS‑4 may have separate terms.
Official launch chart
GPT‑OSS‑120B4,400+
Llama 3.3 70B≈3,700
GLM 4.7 355B≈2,050
GPT‑5.6 Sol≈1,400
Approximate visual reconstruction of the bars published by Cerebras; it is not a new independent measurement.
Approximate visual reading; the image does not replace a benchmark table with complete methodology. Source: Cerebras.
Calculator: how much time you actually save
1.85×output multiplier
3.54 sprevious total time
2.83 snew total time
20.0%end-to-end reduction
With zero fixed latency, 650 → 1,200 reduces the generation time of 1,000 tokens from 1.54 s to 0.83 s: 45.8% less. When fixed steps are added, the total benefit shrinks.
Quality
The same model and weights should preserve quality, but quantization, kernel and configuration can affect results. “Faster” by itself does not make the model smarter.
Reasoning
Reasoning models can generate internal tokens that are not visible. Visible speed does not always reveal all the compute performed.
Agents
When an agent makes 50 sequential calls, saving seconds per call accumulates. There, speed can turn a 90-minute flow into one that is much more interactive.
07
Capacity calculator
How can a 10T or 50T model fit if each wafer has 44 GB?
“Supporting” a distributed model does not mean all of its dense parameters reside simultaneously in the SRAM of a single wafer.
60.0 GBtotal weight memory
2.6 GBactive weights per token, simplified
132 GBaggregate nominal SRAM
Fits nominallyexcluding KV, activations, and reserves
The calculator simplifies: it does not incorporate quantization scales/metadata, embeddings, buffers, KV cache, activations, redundancy, fragmentation, or that SRAM across multiple wafers is not a uniform flat memory. GPT‑5.6 does not publish its exact topology.
10T example: 10 trillion dense parameters in FP16 require about 20 TB; in 4 bits, about 5 TB. Handling that scale needs distribution, pipeline, MoE/sparsity, streaming and external memory. The “more than 50T” claim describes the platform/cluster, not 44 GB magically turned into tens of terabytes.
08
Amdahl for agents
Why 2× more tokens/s does not always make a task 2× faster
An agent task includes network, queue, prefill, reasoning, tools, files, and decode. Only part of it speeds up with the visible token rate.
69.7 sflow at 650 t/s
57.0 sflow at new speed
1.22×end-to-end acceleration
39.6%old time in decode
The opportunity can indeed be enormous: in agents with many sequential calls, saving fractions of a second accumulates. But to capture the full benefit one must also reduce API overhead, scheduling, transfers, tools and time to first token.
09
Compounding
What “doubling speed every year” means
It is not adding 100%; it is multiplying in compound fashion. It must also be distinguished from “triple revenue in 2027”.
Roadmap simulator
24,000 t/s
After 5 doublings: 750 × 2⁵ = 24,000 t/s.
The correct sequence
1× → 2× → 4× → 8× → 16× → 32×
After five years you are not 10× faster: you are 32×, provided each doubling actually happens and the metric is comparable.
It is an aspiration/roadmap, not a guarantee. Management has pointed to a CS‑5 for the second half of 2027 and new systems at roughly double the speed each year for several years. It may depend on new generations, more power, software, networks and disaggregated inference. A valid comparison must hold model, precision, quality, batch, context and methodology constant.
Does the “gap” versus GPU also double?
Not automatically. If Cerebras goes from 1× to 2× but the GPU also improves from 1× to 1.5×, the relative advantage increases only 33%, not 100%. The management phrase mainly describes the speed of each new generation. Turning it into “15× → 30× → 60× versus GPU” wrongly assumes the competitor is frozen.
“More than 20× throughput in 18 months”
It is a third promise, distinct from 2× per user: it can combine more systems, better utilization, separated prefill/decode and capacity expansion. It does not mean a single answer is 20× faster.
“More than triple revenue in 2027”
It is another statement. Taking only as illustration the midpoint of 2026 core guidance of $885 M, tripling exactly would give $2.655 B. “More than triple” would imply a higher figure, but it depends on deployment, customer acceptance and accounting recognition.
10
Silicon
WSE versus GPU: the architectural difference
The potential advantage appears when data trips between chips and external memory shrink.
Conventional GPU cluster
GPUSmall die
HBMVery fast external memory
NetworkNVLink / Ethernet
Many discrete packages are connected. It is flexible, has a huge ecosystem and large HBM capacity, but moving data between packages creates latency, energy and complexity.
Wafer-Scale Engine
1 complete wafer900,000 cores + 44 GB distributed SRAM + on‑wafer network
Cerebras keeps an enormous silicon surface as one logical unit, with extreme internal bandwidth. It reduces many external hops, but requires specialized defect tolerance, cooling, software and manufacturing.
The memory wall
In decode, each token needs to consult enormous weight matrices. The arithmetic can be ready before the data arrive. That is why a large model is usually memory-bandwidth bound: the bottleneck is not multiplying, but feeding the multipliers. Cerebras answers with distributed SRAM and an on‑wafer fabric of tens of PB/s.
WSE‑3T
46,225 mm²
Silicon area per wafer.
Fabric
53.5 PB/s
Per wafer, official figure.
SRAM
44 GB
Very fast, but less capacity than aggregated HBM of a GPU rack.
Essential trade-off: Cerebras wins locality and bandwidth; GPU racks win memory capacity per rack, standardization, CUDA software and availability of a massive ecosystem. The winner depends on the model, the inference phase and the complete economics.
11
Pedagogical microscope
From wafer to core: five zoom levels
To understand Cerebras’s advantage and difficulty, one must distinguish wafer, reticle, logical die, processing and network.
WSE‑3 Turbo
≈46,225 mm²
≈46,225 mm²
A conventional wafer is usually cut into many chips. Cerebras keeps connectivity across the lines that would normally separate those dies.
The scale chain
Wafer
≈300 mm silicon disc
≈300 mm silicon disc
→
Reticles
patterns repeated by lithography
patterns repeated by lithography
→
PE mesh
≈900,000 active cores
≈900,000 active cores
Reticle limit: a lithography machine does not print a 46,000 mm² circuit in a single pass. Regions are exposed and then connections are created between them. That is an important part of the engineering and of the patent portfolio.
What a Processing Element (PE) contains
A PE combines compute, local SRAM memory, a router and program state. Instead of millions of operations traveling repeatedly to distant HBM, the system tries to place data and work nearby and move small “wavelets” across the mesh.
Explore a simplified PE mesh
The orange squares represent an illustrative data path. In the real hardware there are hundreds of thousands of PEs, configurable routing, queues and multiple virtual channels.
12
Yield and redundancy
How can a huge chip work if the wafer has defects?
The answer is not “the wafer comes out perfect”. It is designing granularity, spares, tests and routing to live with defects.
The spare pool absorbs the simulated defect
10defective cells
74illustrative spares
940useful cells
OKreplacement headroom
Do not confuse the simulation with real yield: Cerebras does not publish here an exact production defect rate. The manufacturer describes redundancy and rerouting; any external defect density calculation is illustrative and depends on the node, process, functional area and test criteria.
Why granularity matters
If a defect disables a complete monolithic GPU, a large block is lost. If the system can isolate a small PE and activate a spare, the area lost per defect can be much smaller. But that tolerance requires more silicon, routing, test, defect maps, compiler and validation.
13
The real bottleneck
The memory wall: why moving data can cost more than computing
In decode, the model generates a token, rereads a large part of its weights and repeats. The arithmetic may be waiting on memory.
Conventional GPU: compute ↔ HBM ↔ network
HBM offers enormous capacity and bandwidth, but it sits outside the compute cores and, when a model is split, links among accelerators, switches and racks also appear.
More capacityMature ecosystemHigh flexibility
WSE: distributed SRAM inside the wafer
Local SRAM and a very wide communication mesh reduce distance and latency. The trade‑off is less capacity per area, specialized programming and the need to distribute large models.
Lower latencyExtreme bandwidthLess local capacity
Bandwidth
How many bytes can move per second. Cerebras publishes 43.2 PB/s per wafer; it is an aggregated internal-memory figure, not a direct equivalent of HBM in a full rack.
Latency
How long a datum takes to arrive. A small figure can be decisive in sequential chains, even if another platform’s aggregate throughput is high.
Capacity
How many weights and KV cache fit. Here HBM and system memory keep a practical advantage; that is why streaming, pipeline, MoE and multiple wafers appear.
14
The invisible half
The software that turns a wafer into a useful machine
Copying the shape of the hardware is not enough: graphs, memory, tasks, routes, queues, synchronization and faults must be mapped.
Application / APIChatGPT, agents, voice, code or a scientific application send requests and receive tokens.level 7
ServingRouting, batching, cache, scheduler, admission control, SLA, telemetry and retries.level 6
ModelTransformers, MoE, quantization, speculative decoding, KV management and parallelism.level 5
CompilerIt turns the graph into placement, code, memory and concrete routes on the mesh.level 4
Runtime / hostPython and SdkRuntime load programs, move tensors, launch kernels, and coordinate the system.level 3
CSL + tasksLow-level code by PE regions, asynchronous operations and dataflow triggered by wavelets.level 2
Physical fabricPEs, SRAM, routers, 24 communication colors, queues and links between wafers.level 1
Wavelet and “color”, explained simply
A wavelet is a small data packet. It carries a color tag. That color helps decide where it moves and which task can consume it. It is like a road network with separate logical lanes: congestion in one channel should not necessarily block all the others.
Why a compiler is a moat
On a distributed mesh, choosing where each tensor shard lives and which paths it travels can dramatically change utilization and latency. Years of heuristics, telemetry, placement and debugging do not appear automatically when a wafer is fabricated.
15
System
Nexus, power, cooling, and I/O
CS‑4 is as much a packaging and datacenter-operations innovation as a silicon one.
Wafer-Scale Backpack
Self-contained module with wafer, power conversion, direct liquid cooling, I/O and control. Cerebras claims 50% fewer components and 60% more manufacturing automation.
Official; fleet validation still missing
PowerRack first
The data center can install and certify the stable power, network and cooling layer; then slide in the compute backpack. The company says this reduces deployment from days to hours.
Modular upgrade
Separating compute infrastructure can accelerate maintenance and future generations, provided compatibility, supply and service processes work as promised.
0.5 mm versus ~50 mm
Power conversion is approximately 100× closer to the processor than on a conventional GPU board according to Cerebras. Shorter distance reduces resistive losses and makes it possible to deliver more current. The company states up to double the power to the WSE‑3T to raise frequency.
It does not mean: “it consumes half” nor “the bill drops 100×”. It means the electrical path on the board is shorter and more efficient; total CS‑4 rack power was not published in the datasheet.
New I/O
2.4 Tbit/s per wafer and 7.2 Tbit/s per system. It supports RoCE v2 for Ethernet/RDMA integration and Direct Wafer Links for switchless connections within and between racks, with declared latency of up to 2 μs.
Trade-off: skipping the switch reduces latency, but topology, resilience, operations and failure domains must be evaluated at real scale.
16
From design to datacenter
The manufacturing chain a competitor would have to master
The final product is the result of multiple disciplines; a patent does not replace any of them.
ArchitecturePE, SRAM, fabric, redundancia
→
EDA + masksfloorplan, timing, verification
→
TSMC N5manufacturing and exposure
→
Inter‑diestitching y test
BackpackPCB, connectors, power
→
ThermalsCTE, pressure, cooling
→
Rack NexusI/O, red y servicio
→
OperationSLA, fleet software, clientes
Manufacturing risk
More area, more test points, unconventional packaging, mechanical tolerances and high power. Redundancy reduces the impact of defects, but it does not eliminate cost or complexity.
Deployment risk
Contracted MW are not the same as energized MW. Substations, cooling, racks, network, permits, staff, testing and customer acceptance are needed.
Utilization risk
A very fast rack that sits idle can have poor economics. The scheduler and the mix of loads determine revenue per asset and per megawatt.
17
Heterogeneous inference
Prefill on AMD/AWS, decode on Cerebras
One of the strategically most important parts of the announcement.
Long promptDocuments, code, context
→
AMD Helios / AWS TrainiumPrefill paralelo y compute‑heavy
→
Cerebras CS‑4Ultra-fast sequential decode
Why split
Prefill and decode have different profiles. Placing each phase on the hardware that runs it best can raise utilization and reduce cost.
What is transferred
After prefill, the necessary state must reach the decode engine —including the KV cache or an equivalent representation—. That transfer can be heavy at long contexts.
Success condition
The saving from each phase must beat the latency, bandwidth, and complexity of the handoff. Scheduling, software coherence, and quality reproducibility are decisive.
Why AMD is not necessarily a “competitor” here: the alliance lets Helios sell/occupy prefill and Cerebras decode. It can expand the total market instead of forcing an exclusive choice. The company had indicated solutions with AMD and AWS able to raise throughput by up to 5×, with production milestones planned for Q4 2026 and Q1 2027, respectively.
18
Technical due diligence
How to audit “up to 30×” without falling for marketing
A benchmark is only useful if we understand what was held constant.
Reproducible checklist
0%
Comparison completeness
Check what the benchmark publishes in a verifiable way.
What we know and what is missing
✓
Results by model
The official chart shows from ~1.4k t/s on GPT‑5.6 Sol to ~4.5k on GPT‑OSS‑120B.
✓
Public caveat
Cerebras warns that comparisons are based on internal or third-party tests and that they change by workload and configuration.
?
Complete baseline
The page does not present in a visible table all GPUs, quantities, batch, precision, power and cost of each bar.
?
CS‑4 independence
As of launch day there is not yet an extensive, public and reproducible third-party battery of tests on production CS‑4 hardware.
Useful external signal: Artificial Analysis had already recorded Cerebras as one of the fastest providers for gpt‑oss‑120b, around 1,700 t/s on its measured endpoint. It does not validate CS‑4’s 4,400+, but it does confirm that the architecture’s speed advantage is not purely theoretical.
Why not to compare 750 PFLOPS with 144 PFLOPS and declare a winner
CS‑4 publishes sparse FP16. NVIDIA typically highlights FP4/FP8 for inference, and AMD also publishes FP4/FP8 figures. Each format does different work per operation and can affect quality. Also, a peak specification does not incorporate utilization, memory, interconnect, kernels or model behavior.
| Platform | Useful public datapoint | Why it is not directly comparable |
|---|---|---|
| CS‑4 | 750 PFLOPS sparse FP16; 129.6 PB/s SRAM BW | Wafer‑scale, distributed SRAM, different precision. |
| DGX B200 | 8 GPUs, ~1.44 TB HBM, 64 TB/s aggregated HBM, very high FP4 peak | More memory per node and CUDA stack; different precision and topology. |
| GB300 NVL72 | 72 GPUs, ~20 TB GPU memory, rack-scale NVLink | Much larger rack; comparison should be by workload, energy and cost. |
| AMD MI455X / Helios | 432 GB HBM4 and 23.3 TB/s per GPU; 72 GPUs in Helios | Different generation and software; it can also act as a prefill partner. |
19
Headline audit
What each multiplier means — and what it does not prove
The most frequent error is treating speed, throughput, efficiency, peak compute and model scale as a single metric.
2×
speed per waferGenerational claim: it does not guarantee 2× on every model, context or percentile.
6×
system peak3 wafers × ~2×/wafer. It does not mean a 6× faster conversation.
10×
throughput per wattVersus CS‑3 and under the vendor’s limits/methodology; it is not “10× less bill”.
20×
throughput targetRoadmap through 2027: aggregate capacity, not guaranteed individual speed.
30×
vs GPU solutions“Up to” on selected workloads; a full reproducible matrix is still missing.
50T+
supported parametersDistributed platform scale; not the SRAM capacity of a single wafer.
| Claim | Evidence type | What supports it | What is missing |
|---|---|---|---|
| 3 WSE‑3 Turbo | official | Product page, press release, and datasheet. | Independent physical teardown. |
| >4,400 t/s GPT‑OSS‑120B | vendor | Benchmark shown by Cerebras. | Scripts, prompts, percentiles, precision, quality and full consumption. |
| 650 → 1,200 | interpretation | Consistent with tokens/s, not with price per token. | Exact origin of both numbers and measurement condition. |
| Doubles every year | roadmap | Management statement and CS‑5 planned for 2027. | Silicon, date, yield, software and delivered product. |
| Lower TCO | not demonstrated | The stated efficiency points in that direction. | Rack price, facility kW, utilization, support, useful life and SLA. |
20
There is no single winner
Cerebras versus GPU, TPU, and other accelerators
The useful question is not “which chip is better”, but “which architecture is better for which phase, model, latency, volume and cost”.
Dimension
Cerebras WSE
NVIDIA / AMD GPU
Google TPU
Groq / SRAM dataflow
Strength
Locality, bandwidth and low latency
Ecosystem, flexibility, HBM and scale
Vertical cloud integration and systolic/dataflow
Deterministic decode and low latency
Memory
Distributed SRAM, little local capacity
Large HBM per accelerator/rack
HBM and TPU system memory
SRAM distributed across chips
Programming
Specialized compiler/CSL
Dominant CUDA; growing ROCm
XLA/JAX/TensorFlow
Proprietary compiler
Best fit
Decode and latency-sensitive chains
Training, prefill, batching and general workloads
Workloads integrados en Google Cloud
Fast inference of compatible models
Riesgo
Capacity, portability and economics
Cost/energy and communication between devices
Ecosystem dependence
Capacity/model coverage and commercial scale
The AMD–Cerebras alliance is a clue: the industry can split prefill and decode and use different hardware for each phase. That turns partial competitors into partners inside the same flow.
21
Supernova 2026
What the video adds and what we cannot claim
The event serves as narrative and demonstration; the datasheet and the press release are the verifiable basis of specifications.
Exact timeline
Nasdaq close
CBRS finishes at $220.01, −12.69%.
Supernova starts
Two and a half hours after the regular close.
Keynotes and demos
The full content could not have caused the regular-hours drop retroactively.
Transcript limitation
YouTube blocked automatic transcript extraction in this investigation. For rigor, I do not attribute unverified verbal quotes to the scenario.
Technical points were checked against the same-day press release, the product page and the five-page datasheet. When a figure appears only visually in the chart —such as GPT‑5.6 Sol near 1.4k t/s— it is marked as an approximate reading.
Open original event ↗22
Intellectual property
What protects Cerebras and why it is not easy to copy?
Patents protect concrete claims; the full moat combines IP, secrets, talent, software, manufacturing, operational data and scale.
Patents: legal barrier, not an absolute wall
A competitor cannot validly practice an in-force claim in a covered jurisdiction without a license. But it can design around, challenge, wait for expiration or use another architecture. That is why patents are one layer, not the whole defense.
What the company itself discloses in SEC filings: patents can be challenged, limited, invalidated or designed around. Part of the value depends on confidential knowledge and confidentiality agreements that also do not guarantee perfect protection.
23
Decision tree
“Why don’t NVIDIA, AMD, or a startup copy it?”
Test the question in layers. “Being able to build something similar” and “being able to offer the same profitable product” are different problems.
1. Copy the general idea of using wafer‑scale?
2. Copy exactly patented interconnect, power, mounting or routing?
3. Does it have a compiler, mapping, defect data and fleet operations?
4. Can it deploy MW, win customers and serve with an SLA?
Result
Start with the general idea: wafer‑scale is not a magic word owned by Cerebras. Protection appears in concrete implementations and in all the accumulated know‑how.
The practical barrier
A rival with thousands of engineers and large capital could develop another wafer-scale solution. The problem is time: architecture, tape‑out, yield, packaging, software, customer qualification and datacenter ramp can consume several years, while both sides keep advancing.
The counter-moat
NVIDIA has a barrier of its own: CUDA, libraries, tooling, support, availability and a huge developer base. Cerebras must show that its latency advantage offsets the cost of adopting a less universal stack.
24
Fundamentals
Q2 results, GAAP vs core, and the 2027 promise
The stock does not price only the chip: it prices the ability to turn it into revenue and margin.
GAAP Q2 revenue
$180.1 M
+74% year over year; below the Reuters consensus of ~$194.2 M.
Core Q2 revenue
$209.9 M
+103% year-over-year under the company’s adjusted definition.
Gross margin
14% / 41%
GAAP versus core; a huge presentation difference.
RPO
$25.4 B
Remaining performance obligations, not cash collected today.
How can it “beat” and “miss” at the same time?
GAAP: $180.1 M, a comparable accounting figure that Reuters set against a $194.2 M consensus; that is why it appears as a miss.
Core: $209.9 M, a management-adjusted measure that removes/reallocates certain items; it can beat another expectation.
Both sentences can be true. The investor should read the reconciliation, not pick the figure that confirms the thesis.
What explains the post‑results drop
GAAP revenue miss, lower core margin, weak hardware, heavy investment for cloud and extremely high expectations. Cloud grew about four times and reached ~$126 M, but the model requires financing capacity before recognizing much of the revenue.
The market asked: “can it scale profitably?”, not “is there demand for AI?”.
RPO is not guaranteed immediate revenue
$25.4 B RPOContract / future obligation
→
Build capacityCapital, energy, racks, supply
→
Deliver and recognizeUsage, SLA, milestones, accounting
The 10‑Q also shows customer concentration, terms and warrants associated with strategic agreements. The potential is enormous, but conversion requires capacity, milestone delivery and effective demand.
25
RPO, MW y reconocimiento
From a US$25.4B contract to real revenue: the missing bridge
RPO is a future performance obligation. It is not cash received or an assured profit.
Simplified economic flow
Contract / commitment
Capacity, price, milestones, service, and options are agreed.
Financing and construction
Wafers, racks, data centers, energy, network and staff.
Acceptance / availability
The customer tests performance, reliability, and SLA.
Consumption and recognition
The service is delivered and accounting recognizes revenue according to terms.
Cash and margin
It is collected, net of capacity cost, operations, depreciation and financing.
Time reading of disclosed RPO
Approximate distribution communicated in the 10‑Q; actual timing may vary by milestones, capacity, usage and contractual modifications.
Concentration: two customers accounted for a very high share of reported accounts receivable. A large contract validates demand, but it also concentrates execution and counterparty risk.
26
Unit economics
The equation that actually has to win: dollars and margin per megawatt
Tokens/s is an input. The business needs to transform hardware and energy into sold service with utilization and margin.
$292.5 Millustrative annual revenue
$122.9 Millustrative gross profit
35 MWequivalent idle capacity
$4.50 Mrevenue per active MW
It is not a forecast. Cerebras does not publish all the inputs needed for a complete unit-economics model. The calculator shows why utilization and margin can matter as much as peak performance.
27
CBRS
Why it rises 15% and then falls 13–20%
It is a young stock, high duration, high multiple, with news that quickly changes the distribution of future outcomes.
Daily closes
$226.93 → $220.01
Between 7 and 18 August: little net change, but with extreme swings.
CBRSDaily riseDaily drop
| Date | Close | Day | Dominant catalyst | Cautious reading |
|---|---|---|---|---|
| 7 Aug | $226.93 | +7.40% | Run-up before results | Expectations rising ahead of the print. |
| 12 Aug | $262.06 | +11.63% | Rally before Q2; results after the close | The stock entered the report with a very high bar. |
| 13 Aug | $231.01 | −11.85% | Digestion of the GAAP miss and margin | Good guidance did not offset profitability doubts. |
| 14 Aug | $218.98 | −5.21% | Continuation; GPT‑5.6 Ultrafast announcement | Technical validation did not erase the financial repricing. |
| 17 Aug | $251.98 | +15.07% | Rebound, OpenAI, analysts and CS‑4 anticipation | Re-expansion of execution probability. |
| 18 Aug | $220.01 | −12.69% | Semi selloff + de‑risking + potential technical supply | The event started after the close. The 10‑Q also warned that up to 1.2 M shares could be sold around this date to cover RSU taxes. |
1. Macro / sector
On August 18 SOXX fell ~5.0%, AMD ~4.2% and NVIDIA ~2.4%. Yields and oil rose in a U.S.–Iran tension environment. That compressed semiconductor multiples.
2. High narrative beta
CBRS is a recent IPO, with little history and extraordinary growth expectations. Each news item moves not only the next quarter, but the probability of capturing a share of the inference market.
3. Sensitive valuation
With an approximate market cap of $52.3 B and 2026 core guidance of ~$885 M, the simple multiple is around 59× sales. At that level, a small change in confidence produces a large change in price.
4. Potential technical supply the same day: the 10‑Q estimated that up to 1.2 million shares could be sold in the market “around August 18” to cover tax withholdings associated with quarterly RSU vesting. This does not prove causation —we do not know how many were sold or the exact flow— but it may have added supply pressure to an already-weak sector session.
Paradoxical result: from the August 14 close ($218.98) to the 18th ($220.01), the stock was barely +0.47%. The +15.07% and the −12.69% almost canceled out. Volatility was enormous, but the net change was minimal.
Post-event reading: extended-hours quotes available at the end of the session placed CBRS roughly between $217 and $220, that is, from almost flat to around −1.3% versus the close. A second move comparable to the −12.69% regular-session drop did not appear; the range is approximate because after‑hours providers showed differences.
28
Causal chronology
Which news was available at each moment of the move
So as not to attribute a drop retrospectively to an event that had not yet occurred.
Q2: GAAP vs “core” shock
The cloud business is growing strongly, but GAAP revenue and margin raise doubts. The stock falls in extended hours.
Repricing and digestion
The market processes margin, hardware, and extremely high expectations.
+15.07%
Enthusiasm for OpenAI Ultrafast, analyst comments and anticipation of Supernova/CS‑4.
−12.69%
Broad semiconductor selloff, yields and oil; reversal of the prior rally; possible technical RSU supply.
Supernova starts
The event occurs 2 h 30 min after the regular close. By definition, it could not explain the entire session drop.
CS‑4 publication
The market starts to evaluate product, roadmap, manufacturing and how much was already discounted.
Attribution model, not certainty
35%
Sector / macro
SOXX fell around 5%; semiconductors and technology were the epicenter.
30%
Reversal and positioning
After +15% in a day, stops, profit‑taking and low liquidity amplify.
25%
Specific risk
Margin, execution, valuation and post-Q2 doubts.
10%
Possible technical supply
The 10‑Q contemplated sales to cover RSU taxes; the amount actually sold is not known.
The percentages are a pedagogical frame, not an observed statistical decomposition. Daily moves do not have a single cause measurable with precision.
29
Sensibilidad
Valuation calculator
It does not predict the price; it shows why a high-multiple stock reacts violently to small changes.
$52.27 Bapproximate market capitalization
59.1×market cap / 2026 sales
$2.66 Billustrative 2027 sales
19.7×multiple on 2027
It is a market-cap calculation, not enterprise value. It does not net cash/debt, does not incorporate future dilution, warrants, SBC or differences between GAAP/core revenue. It is for intuition only.
Why the technology can be good and the stock can fall
A company can launch an excellent product, but if the price already assumed an extraordinary launch, the news only confirms the base case. Stock returns depend on the difference between reality and expectations, not only on absolute quality.
What the multiple needs to justify
Fast RPO conversion, massive production, high utilization, expanding margin, financeable capex, lower concentration, sustained adoption and an advantage that survives NVIDIA/AMD and future generations.
30
Escenarios
Bull, base, and bear theses
The most honest way to analyze such a new company is to think in conditions, not certainties.
🟢 Bull
CS‑4 ships in production; OpenAI validates the platform; AMD/AWS disaggregated designs lift utilization; capacity grows >10×; RPO converts; 2027 exceeds 3× revenue and margin improves.
What would confirm it
Independent benchmarks, additional customers, mass availability, revenue conversion, rising gross margin and disciplined capex.
🔵 Base
The technology keeps a clear advantage in decode, but deployment takes time, the cloud mix pressures margins and GPU partners still dominate much of the stack. High growth with extreme volatility.
What would confirm it
Gradual ramp, milestones met with minor delays, stabilized margin and adoption focused on agents/latency.
🔴 Bear
The “up to” figures do not replicate in real TCO; capacity/reliability delay revenue; concentration and warrants weigh; NVIDIA/AMD close the gap; the required capital erodes return and the multiple compresses.
What would confirm it
Cut guidance, unconverted RPO, lower utilization, stalled margin, capex above plan or unfavorable normalized benchmarks.
My balanced reading
Technically significant product; equity thesis still dependent on exceptional execution.
CS‑4 improves Cerebras’s credibility as a serious alternative for low-latency inference. It does not by itself resolve the hardest questions: total cost, production, reliability, utilization, margin, concentration and competitive response.
31
Upcoming milestones
What to watch from today
A board for separating real progress from headlines.
Technical / product
Financial / commercial
The metric that matters: it will not be the max tokens/s on a slide. It will be how much revenue and margin each megawatt and each dollar of deployed capital generates, with real customers and sustainable SLAs.
32
Anti-hallucination
12 myths this report corrects
Click to flip each card.
“CS‑4 is a CPU”
No. It is an AI-specialized rack-scale system that integrates three wafer-scale accelerators.
“WSE‑4 was launched”
Not necessarily. The system is called CS‑4 and uses WSE‑3 Turbo.
“6× = a 6× faster response”
No. 6× is the approximate aggregate peak of 3 wafers × 2× per wafer.
“10× per watt = 10× less electricity”
No. Load, system, cooling, utilization and facility cost still need to be bounded.
“30× across the board”
No. It is “up to” in selected comparisons; the complete methodology matters.
“50T fits in 44 GB”
No. It is a distributed platform capability using multiple techniques and systems.
“1,200 is the new price”
They are almost certainly tokens per second. Price is published in US$/million tokens.
“Patent = impossible to copy”
No. A patent can be designed around, challenged or expire; it protects concrete claims.
“RPO = cash”
No. It is future contracted work pending performance and recognition.
“The event caused the entire drop”
No: it started after the regular close of the session that fell 12.69%.
“More t/s = better model”
No. Hardware speed does not automatically change intelligence, quality or safety.
“GPU and WSE cannot coexist”
Yes they can: prefill on GPU and decode on WSE is precisely an announced strategy.
33
How it was built
Methodology, controls, and limits
An exhaustive investigation is not accumulating links; it is knowing what each source can prove.
Source hierarchy
- Regulatory documents: contracts, risks, shares, accounting.
- Official technical documents: stated specifications and architecture.
- Academic/independent literature: mechanisms, limits and reproducibility.
- Financial press: consensus, reaction and context.
- Market data: prices, volume and sector.
Four audit filters
- Is the figure peak, average, percentile or “up to”?
- Does the comparison use the same model, precision, context and quality?
- Is it a current result, a derived calculation or a future target?
- Does the source have a commercial interest or methodological limitations?
Uncertainty map
High confidenceName, components, published specifications, dates, and SEC figures.
MediumPlausible technical mechanism supported by literature, without independent CS‑4.
Forward‑lookingCS‑5, annual doubling, 20× throughput, 600 MW and >3× revenue.
UndisclosedCS‑4 price, facility power, real volume, TCO, p95/p99 and yield.
This is not financial advice. An outstanding technology can be a bad investment at a certain price; a volatile stock can rise or fall for factors not identifiable in real time.
34
Quick lookup
Searchable glossary
Type “memory”, “latency”, “RPO” or any term.
TokenMinimum unit the model processes or generates.
InferenceRunning an already-trained model to produce answers.
PrefillPhase that processes the full prompt/context in parallel.
DecodeSequential phase that generates one token after another.
TTFTTime from sending the request to receiving the first token.
ITLLatency between consecutive tokens.
ThroughputTotal sustained work per unit of time.
LatencyTime a request or a part of the system takes.
WSEWafer-Scale Engine: a processor that uses almost an entire wafer.
SRAMVery fast, expensive memory close to compute.
HBMHigh-bandwidth stacked memory used by GPUs.
FabricInternal network connecting cores and memory.
PFLOPS10¹⁵ floating-point operations per second; the precision context matters.
Sparse FP16FP16 peak assuming exploitable sparsity; not equivalent to real dense FP16.
MoEMixture of Experts: many total parameters, few experts active per token.
KV cacheState generated while reading the context and reused during decode.
RoCE v2RDMA over Ethernet for low-latency transfers.
TCOTotal cost: hardware, energy, cooling, network, support and operations.
GAAPStandardized U.S. accounting.
Core / adjustedNon-GAAP metric defined by the company; requires reconciliation.
RPOContractual performance obligations not yet recognized as revenue.
SBCStock-based compensation; economic cost and potential dilution.
Market capPrice per share multiplied by economic shares.
De‑riskingReduce exposure before an uncertain event.
AcceleratorSpecialized processor for running AI operations more efficiently than a general CPU.
ReticleMaximum area exposed in one pass of the lithography system; wafer-scale requires connecting multiple regions.
Reticle stitchingTechniques for creating electrical connections between exposure regions/logical dies on the wafer.
Processing Element (PE)Small unit with compute, local memory, router and program state.
WaveletA 32-bit data packet that travels the WSE fabric and can activate tasks.
ColorVirtual routing channel/tag used to separate wavelet streams.
DSDCSL data-structure descriptor for describing memory or streams that enter/leave.
AOT compilationAhead-of-time compilation of the graph before execution; it can optimize a lot but reduces dynamism.
Reticle yieldShare of useful functional units after manufacturing and test; it is not equivalent to yield of a complete wafer.
Defect mapMap of defective components used to activate redundancy and avoid them.
CTECoefficient of thermal expansion; silicon, PCB and metal change size differently with temperature.
RDMADirect remote memory access with low CPU involvement.
RoCE v2RDMA transported over routable Ethernet.
Speculative decodingA small model proposes tokens that the main model verifies in parallel.
BatchingGrouping requests to improve utilization and throughput, sometimes at the cost of latency.
ConcurrencyNumber of simultaneous requests served.
p50 / p95 / p99Latency percentiles: 95% or 99% of requests finish below that value.
Power envelopePower limit to sustain frequencies, temperature and reliability.
DepreciationAccounting allocation of an asset’s cost over its useful life.
Sell-to-coverAutomatic sale of shares to pay taxes when stock-based compensation vests.
ReroutingDivert communications around defective or congested components.
PlacementAssignment of operations and data to concrete physical locations.
NoCNetwork-on-Chip, internal communication network among compute units.
Direct Wafer LinkProprietary link between wafer-scale modules for a distributed pipeline.
NexusModular architecture of the CS-4 that separates stable infrastructure and replaceable compute modules.
35
Active learning
Check that you have it
Five questions with immediate explanation.
1. Does 650 → 1,200 on GPT‑5.6 refer mainly to…?
2. Why does CS‑4 have 6× system compute but up to 2× speed per wafer?
3. “Up to 30×” means…
4. On August 18, was the regular-session drop a reaction to the full keynote?
5. What best tests the financial thesis?
36
Traceability
Sources, methodology, and limits
Curated library of 100 primary, regulatory, academic, patent, competitor and market sources. Quantity does not replace the hierarchy of evidence.
S01
Cerebras — CS‑4 product pageOfficialSpecifications, claims, Nexus, and benchmark caveats.
S02
Cerebras — CS‑4 press releaseOfficialLaunch, WSE‑3 Turbo, performance, I/O and shipments.
S03
Cerebras — CS‑4 datasheetOfficialOfficial system datasheet.
S04
Supernova 2026 — livestreamOfficialPublic presentation of CS‑4 and roadmap.
S05
IR — Supernova livestream announcementOfficialOfficial event time.
S06
Cerebras — AMD + Cerebras disaggregated inferenceOfficialPrefill on AMD, decode on WSE, and an efficiency target.
S07
Cerebras — 100× defect toleranceOfficialManufacturer explanation of defects and redundancy.
S08
Cerebras SDK — main documentationOfficialArchitecture, CSL, tutorials and APIs.
S09
Cerebras SDK — conceptual viewOfficialPEs, wavelets, colors and dataflow programming.
S10
Cerebras SDK — release notesOfficialSoftware evolution and WSE-3 support.
S11
Cerebras SDK — SdkRuntime APIOfficialHost runtime, load, execution and transfers.
S12
Cerebras SDK — SdkLayout APIOfficialRegions, colors and layout.
S13
Cerebras SDK — advanced featuresOfficialRouting, switching and color control.
S14
Cerebras SDK — examplesOfficialCSL examples and reproducible benchmarks.
S15
Cerebras Cloud SDK PythonOfficialOfficial inference API client.
S16
Cerebras SDK technical overviewOfficialWhitepaper on CSL, DSDs, and fabric.
S17
Cerebras — HPC with SDKOfficialAccessible explanation of wavelets and tasks.
S18
Cerebras product chipOfficialWSE‑3 background and specifications.
S19
Cerebras InferenceOfficialCloud inference offering and use cases.
S20
Cerebras inference docsOfficialAPI, models and serving parameters.
S21
Cerebras cloudOfficialAccess to the inference service.
S22
Cerebras IR — press releasesOfficialOfficial announcement history.
S23
Cerebras IR — investor relationsOfficialResults, SEC, and events.
S24
Cerebras publicationsOfficialTechnical publications and case studies.
S25
Cerebras blogOfficialManufacturer technical context.
S26
Q2 2026 results releaseSEC/IRGAAP, core, guidance, RPO and capacity.
S27
Cerebras Q2 2026 Form 10‑QSEC/IRContracts, risks, concentration, debt, shares and RSUs.
S28
SEC company filings — CerebrasSEC/IRPrimary regulatory source.
S29
SEC Inline XBRL factsSEC/IRRegulatory filings and financial statements.
S30
Cerebras IR — SEC filingsSEC/IRIndex of filings.
S31
Cerebras IR — quarterly resultsSEC/IRQuarterly results and materials.
S32
Cerebras IR — stock informationSEC/IRCorporate stock data.
S33
Cerebras IR — eventsSEC/IRPresentations and events.
S34
Cerebras IR — governanceSEC/IRGovernance and corporate documents.
S35
Nasdaq — CBRSSEC/IRQuote and corporate reference.
S36
OpenAI partners with CerebrasOpenAI750 MW and a low-latency strategy.
S37
Previewing GPT‑5.6 Sol UltrafastOpenAIUp to 750 output t/s and limited availability.
S38
GPT‑5.6 launch and pricingOpenAIModels, capabilities and price per million tokens.
S39
GPT‑5.6 full-stack efficiencyOpenAIRouting, kernels, caching and speculative decoding.
S40
WebSockets for agentic workflowsOpenAIHow API overhead limits >1,000 t/s.
S41
Introducing gpt‑ossOpenAIOpen model and multi-hardware optimization.
S42
gpt‑oss‑120b model cardOpenAIParameters, MoE, precision and context.
S43
OpenAI API pricingOpenAICurrent API prices.
S44
OpenAI + Broadcom JalapeñoOpenAIMulti-accelerator strategy and future competition.
S45
US 12,705,112 — placement of linear operatorsPatentPlacement and mapping on PE arrays.
S46
US 12,625,745 — optimized placementPatentOptimized placement for efficiency.
S47
US 12,463,139 — multi-die interconnect lithographyPatentInterconnect between dies/reticles.
S48
US 12,314,218 — task synchronizationPatentDataflow task synchronization.
S49
US 12,217,147 — advanced wavelet filteringPatentWavelet filtering and routing.
S50
US 12,204,954 — placement compute/memoryPatentPhysical assignment of compute and memory.
S51
US 12,177,133 — dynamic routingPatentDynamic routes around conditions/faults.
S52
US 12,169,771 — wavelet filteringPatentChannel and data filtering.
S53
US 11,934,945 — accelerated deep learningPatentAccelerated deep-learning architecture.
S54
US 11,853,867 — task activatingPatentTask activation by streams.
S55
US 11,727,254 — control waveletPatentControl wavelets.
S56
US 11,727,257 — data structure descriptorsPatentData-structure descriptors.
S57
US 11,631,600 — securing componentsPatentMechanical fastening of components.
S58
US 11,626,342 — sliding thermal interfacePatentThermal interface with differential expansion.
S59
US 11,488,004 — neuron smearingPatentDistribution of neurons/operators.
S60
US 11,475,282 — microthreadingPatentMicrothreads and execution.
S61
US 11,449,574 — stochastic roundingPatentNumerical precision.
S62
US 11,367,686 — multi-die interconnectionPatentConnections across scribe lines.
S63
US 11,328,208 — processor redundancyPatentReplacement of defective PEs.
S64
US 10,840,216 — power-on-waferPatentPower delivery and assembly.
S65
US 10,923,412 — sliding thermal interfacePatentThermal expansion management.
S66
Justia — portfolio CerebrasPatentPatent portfolio index.
S67
WaferLLMAcademicLLM inference on WSE‑2; mapping, GEMM/GEMV, and KV cache.
S68
Wafer-scale integration reviewAcademicSurvey of architectures, yield, packaging, and trade‑offs.
S69
WSE vs NVIDIA systems comparisonAcademicArchitecture comparison and viability.
S70
MLIR lowering for wafer-scale stencilsAcademicCompiler and portability to WSE‑2/WSE‑3.
S71
SPADA programming languageAcademicSpatial dataflow abstractions over CSL.
S72
Field-equation API for WSEAcademicHigh-level API and HPC.
S73
2D Ising model on WSEAcademicScientific application and scaling.
S74
Elk — inter-core AI chipsAcademicAnalysis of chips with distributed memory and interconnect.
S75
Ouroboros wafer-scale SRAM CIMAcademicMapping/communication alternatives and limits.
S76
SHIFT compute relocationAcademicWafer-scale architectures and compute movement.
S77
Systematic study of LLM serving on multi-core NPUsAcademicMemory, placement, PD disaggregation and serving.
S78
WATOS wafer-scale LLM trainingAcademicArchitecture and training co-design.
S79
Speculative decodingAcademicBasis for accelerating decode with draft models.
S80
vLLM / PagedAttentionAcademicGPU serving and KV cache management.
S81
DistServeAcademicPrefill and decode disaggregation.
S82
NVIDIA GB300 NVL72CompetitorRack-scale GPU platform reference.
S83
NVIDIA DGX B200CompetitorGPU system and official specifications.
S84
NVIDIA CUDACompetitorDominant software ecosystem.
S85
AMD Instinct MI455XCompetitorAccelerator and Helios platform.
S86
Google Cloud TPU architectureCompetitorArchitecture and TPU topology.
S87
Groq LPUCompetitorDataflow/SRAM inference accelerator.
S88
AWS TrainiumCompetitorAWS accelerators for AI.
S89
TSMC 5 nm technologyStandardN5 manufacturing node.
S90
RoCE InitiativeStandardRDMA over Converged Ethernet.
S91
Reuters — Q2 results reactionMarketConsensus, margin and after-hours reaction.
S92
Reuters — Q2 mixed resultsMarketContext of expectations and hardware.
S93
Reuters — tech selloff Aug 18MarketSector, yields, oil and macro risk.
S94
Reuters — CS‑4 launchMarketIndependent reading of the announcement.
S95
Investors.com — CS‑4MarketProduct, market and stock.
S96
MarketWatch — CS‑4 and valuationMarketScale, expectations, and risks.
S97
Investors.com — semiconductor selloffMarketSector drop of August 18.
S98
StockAnalysis — CBRS historyMarketDaily historical prices.
S99
MarketWatch — CBRS quoteMarketQuote and news.
S100
Artificial AnalysisMarketSpeed and quality of inference endpoints.
How to read this library
PrimaryIt proves what the company or regulator stated, not necessarily that the claim is universal.
Vendor benchmarkUseful as a signal; requires full methodology and replication.
IndependentIt can validate mechanisms, but may use WSE‑2 or another workload.
MarketExplains context and consensus; it does not prove exact price causality.
Mode: From zero · Engineering · Investor · Auditor · Search any term above